Self-aligned dual-floating gate memory cell .

ABSTRACT

An integrated circuit that includes a first dual-floating gate memory cell having a first floating gate isolated from a second floating gate for storing at least one bit of datum, and a second dual-floating gate memory cell having a third floating gate isolated from a fourth floating gate for storing at least one bit of datum, wherein the first dual-floating gate memory cell and the second dual-floating gate memory cell share a control gate, wherein the second floating gate of the first dual-floating gate memory cell shares an oxide layer with the third floating gate of the second dual-floating gate memory cell, and wherein the oxide layer electrically insulates the second and third floating gates from the control gate.

DESCRIPTION OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention pertains in general to a semiconductor device and,more particularly, to a dual-floating gate memory cell and method formanufacturing the same.

[0003] 2. Background of the Invention

[0004] A non-volatile memory cell, such as a flash memory cell, withmultiple floating gates to store multiple bits of data is known. Such amemory cell generally includes two floating gates to store two bits ofdata, and each bit of datum may be stored (programmed) and readindividually. U.S. Pat. No. 5,929,480 describes a non-volatilesemiconductor memory device having first and second floating gates.However, due to the complexity of some of the known dual-storage memorycell structures, these memory cells cannot be easily scaled, whichpresents a major obstacle to commercialization. Furthermore, the methodsfor manufacturing these conventional dual-storage memory cells arecomplicated and costly. Therefore, there is a need for a dual-storagememory cell with excellent scalability and may be manufactured usingexisting CMOS technology to minimize cost.

SUMMARY OF THE INVENTION

[0005] In accordance with the invention, there is provided an integratedcircuit that includes a first dual-floating gate memory cell having afirst floating gate isolated from a second floating gate for storing atleast one bit of datum, and a second dual-floating gate memory cellhaving a third floating gate isolated from a fourth floating gate forstoring at least one bit of datum, wherein the first dual-floating gatememory cell and the second dual-floating gate memory cell share acontrol gate, wherein the second floating gate of the firstdual-floating gate memory cell shares an oxide layer with the thirdfloating gate of the second dual-floating gate memory cell, and whereinthe oxide layer electrically insulates the second and third floatinggates from the control gate.

[0006] In one aspect, one of the first, second, third and fourthfloating gates has a vertical dimension greater than or equal to ahorizontal dimension.

[0007] In another aspect, the integrated circuit further includes afirst isolation oxide to isolate the first floating gate from the secondfloating gate.

[0008] Also in accordance with the present invention, there is provideda method for manufacturing a semiconductor device that includes defininga substrate, providing a dielectric layer over the substrate, depositinga first layer of polysilicon over the dielectric layer, providing alayer of nitride over the first layer of polysilicon, forming aplurality of composite structures, each having a section of the firstpolysilicon layer and nitride layer, forming a plurality of diffusedregions in the substrate between the plurality of composite structures,forming isolation oxides between the plurality of composite structures,removing the sections of the nitride layer, forming a plurality ofspacers over the first polysilicon layer and contiguous with sidewallsof the isolation oxides, etching the first polysilicon layer with theplurality of spacers acting as masks, removing the plurality of spacers,forming a layer of inter-gate dielectric over the etched firstpolysilicon layer, and forming a second polysilicon layer over theinter-gate dielectric layer.

[0009] In one aspect, the step of forming a plurality of spacersincludes forming a plurality of oxide spacers.

[0010] In another aspect, the step of forming a plurality of spacersincludes forming a plurality of polysilicon spacers.

[0011] Further in accordance with the present invention, there isprovided a method for manufacturing a semiconductor device that includesdefining a substrate, forming a dielectric layer over the substrate,depositing a first layer of polysilicon over the dielectric layer,providing a layer of nitride over the first layer of polysilicon,etching the layer of nitride and the first layer of polysilicon to forma plurality of composite structures, each having a section of the firstpolysilicon layer and nitride layer, depositing a layer of oxide usinghigh-density plasma deposition over and between the plurality ofcomposite structures, removing the nitride layer, forming a plurality ofspacers over the first polysilicon layer, etching the first polysiliconlayer with the plurality of spacers acting as masks, removing theplurality of spacers, forming an inter-gate dielectric layer over theetched first polysilicon layer, and forming a second polysilicon layerover the inter-gate dielectric layer.

[0012] Additional objects and advantages of the invention will be setforth in part in the description which follows, and in part will beobvious from the description, or may be learned by practice of theinvention. The objects and advantages of the invention will be realizedand attained by means of the elements and combinations particularlypointed out in the appended claims.

[0013] It is to be understood that both the foregoing generaldescription and the following detailed description are exemplary andexplanatory only and are not restrictive of the invention, as claimed.

[0014] The accompanying drawings, which are incorporated in andconstitute a part of this specification, illustrate several embodimentsof the invention and together with the description, serve to explain theprinciples of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015]FIG. 1 is a cross sectional view of an integrated circuitconsistent with the present invention; and

[0016] FIGS. 2-9 are cross sectional views of a method for manufacturingan integrated circuit consistent with the present invention.

DESCRIPTION OF THE EMBODIMENTS

[0017] Reference will now be made in detail to the present exemplaryembodiments of the invention, examples of which are illustrated in theaccompanying drawings. Wherever possible, the same reference numberswill be used throughout the drawings to refer to the same or like parts.

[0018] In accordance with the present invention, there is provided aself-aligned dual-floating gate memory cell and method for manufacturingthe same. Each of the self-aligned dual-floating gate memory cells ofthe present invention is capable of storing at least two bits of data,and each bit of datum in the memory cell is programmed and readseparately. FIG. 1 is a cross sectional view of an integrated circuitconsistent with the present invention. Referring to FIG. 1, anintegrated circuit 10 includes a substrate 12, such as silicon, and aplurality of diffused regions 18, 20 and 22 formed therein. The diffusedregions 18, 20 and 22 may be n-type or p-type regions. A dielectriclayer 24, comprising materials such as silicon dioxide, silicon nitride,and/or silicon oxynitride, is formed over the substrate 12. Thedielectric layer 24 is sometimes known as a tunnel oxide. The integratedcircuit 10 also includes a first self-aligned dual-floating gate memorycell 14 and a second self-aligned dual-floating gate memory cell 16 ofthe present invention. The integrated circuit 10 may additionallyinclude other self-aligned dual-floating gate memory cells, but onlypartially shown in FIG. 1.

[0019] The first self-aligned dual-floating gate memory cell 14 includesa first floating gate 30 to store one bit of datum and a second floatinggate 32 to store a second bit of datum. The floating gates 30 and 32 aredisposed over the dielectric layer 24. The first memory cell 14 alsoincludes a control gate 48, electrically insulated from the firstfloating gate 30 with a first inter-gate dielectric 42 and the secondfloating gate 32 with a second inter-gate dielectric 44. The firstinter-gate dielectric 42 is contiguous with the top and one side of thefirst floating gate 30, and the second inter-gate dielectric 44 iscontiguous with the top and one side of the second floating gate 32. Thefirst memory cell 14 further includes source/drain regions 18 and 20,and a channel region (not numbered) disposed therebetween. One skilledin the art understands that it is not important how the source/drainregions 18 and 20 are labeled. In addition, as described below,inter-gate dielectric layers 40, 42, 44, and 46 are comprised of thesame material and formed at the same time during the manufacturingprocess. In addition, inter-gate dielectric layers 40, 42, 44, and 46may be a continuous dielectric layer.

[0020] The second self-aligned dual-floating gate memory cell 16includes a first floating gate 34 and a second floating gate 36,insulated from the substrate 12 by the dielectric layer 24. The secondmemory cell 16 shares the same control gate 48 with the first memorycell 14. The control gate 48 is electrically insulated from the firstfloating gate 34 with the second inter-gate dielectric 44 and the secondfloating gate 36 with a third inter-gate dielectric 46. The secondinter-gate dielectric 44 is contiguous with the top and one side of thefirst floating gate 34, and the third inter-gate dielectric 46 iscontiguous with the top and one side of the second floating gate 36. Inaddition, the second floating gate 32 of the first memory cell 14 sharesthe same inter-gate dielectric 44 with the first floating gate 34 of thesecond memory cell 16. The second memory cell 16 further includessource/drain regions 20 and 22, and a channel region (not numbered)disposed therebetween. Each of the floating gates 34 and 36 is capableof storing at least one bit of datum. Floating gates 26 and 38 representparts of other self-aligned dual-floating gate memory cells.

[0021] The floating gates 28 and 30, 32 and 34, and 36 and 38 areelectrically insulated from each other with isolation oxides 50. Inaddition, each of the floating gates 28, 30, 32, 34, 36 and 38 has ahorizontal dimension, or width, “a” and a vertical dimension, or height,“b”. The gate coupling ratio (GCR) of a floating gate indicates thescalability of the integrated circuit, and the greater the GCR, thegreater the scalability of the integrated circuit. The GCR may beapproximated as$\frac{\left( {a + b} \right)}{\left( {{2a} + b} \right)}.$

[0022] Therefore, the GCR may be increased, for example, by decreasingthe width “a”. In one embodiment, the height of the floating gates isgreater than or equal to the width, i.e., b≧a.

[0023] In operation, the self-aligned dual-floating gate memory cells ofthe present invention may be programmed by mid-channel hot-electroninjection. As an example, referring again to FIG. 1, the memory cell 14may be programmed by first programming a first bit, e.g., floating gate30, and then a second bit, e.g., floating gate 32, or vice versa. Toprogram the first bit, a high voltage, e.g., 8 volts, is provided to thecontrol gate 48, and the source/drain region 18 is coupled to ground.The other source/drain region 20 is provided with a potential lower thanthat of the control gate, e.g., 4 volts. To program the second bit, ahigher voltage, e.g., 8+ΔVt volts, is provided to the control gate 48,and the source/drain region 20 is coupled to ground. The othersource/drain region 18 is provided with a potential lower than that ofthe control gate, e.g., 4 volts.

[0024] The memory cells of the present invention may be erased bychannel erase or band-to-band induced hot holes. As an example, tochannel erase the memory cell 14, each of the source/drain regions 18and 20 is provided with a high voltage, e.g., 8 volts. The substrate 12is provided with the same high voltage, and the control gate 48 isprovided with a high negative voltage, e.g., −8 volts. The electrons areerased through the channel between the source/drain regions 18 and 20.The memory cell 14 may also be erased with band-to-band induced hotholes. In operation, the substrate 12 is grounded, the source/drainregions 18 and 20 are provided with a potential of 4 volts, and thecontrol gate 48 is provided with a potential of −8 volts.

[0025] Finally, the first bit of the memory cell 14 may be read byapplying 3 volts to the control gate 48, 1.5 volts to the source/drainregion 18 and a ground potential to the source/drain region 20.Conversely, the second bit of the memory cell 14 may be read by applying3 volts to the control gate 48, 1.5 volts to the source/drain region 20and a ground potential to the source/drain region 18.

[0026] FIGS. 2-7 are cross sectional views of a method for manufacturingan integrated circuit having self-aligned memory cells consistent withthe present invention. Referring to FIG. 2, conventional CMOSmanufacturing processes may be used to define a substrate 12, form theshallow trench isolations (not shown), and define p-wells and n-wells(not shown). A dielectric layer 24 is then formed over the substrate 12.A first layer of polysilicon 26 is deposited over the dielectric layer24. A layer of nitride 52 is then deposited over the first layer ofpolysilicon 26. The structure comprising the first layer of polysilicon26 and layer of nitride 52 is masked, patterned, and etched to form aplurality of composite structures having sections of the firstpolysilicon layer 26 and nitride layer 52. The mask is then removed.With the composite structures acting as masks, impurities are implantedinto the exposed areas of the substrate 12 to form a plurality ofdiffused regions 18. The diffused regions 18 later become source/drainregions of memory cells. A step of oxidation anneal follows, in part, todiffuse the regions 18 further into the substrate 12.

[0027] Referring to FIG. 3, high-density plasma (HDP) oxide depositionis performed to coat the entire integrated circuit structure with oxide,forming an oxide layer 50. The HDP deposition process is capable offilling the areas between the composite structures to provide adequateisolation between the composite structures. In addition, because of theinherent simultaneous deposition and etching characteristics of the HDPdeposition process, a plurality of peaks, or bumps, are formed on thetop surface of the oxide layer 50. Referring to FIG. 4, these peaks areremoved by chemical-mechanical polishing (CMP), with the sections of thenitride layer 52 acting as polish stop.

[0028] Referring to FIG. 5, after the CMP, the sections of the nitridelayer 52 are removed. Oxide chemical-vapor deposition (CVD) follows tocoat the entire integrated circuit structure with oxide. A step of oxidespacer etch then follows to form a plurality of oxide spacers 56. Theoxide spacers 56 are formed over the sections of the first polysiliconlayer 26 and contiguous with the sidewalls of the isolation oxides 50.As shown in FIG. 6, using the oxide spacers 56 as masks, the sections ofthe first polysilicon layer 26 is etched further to form additionalsections of the first polysilicon layer 26. Each of the further etchedsections of the first polysilicon layer 26 becomes a floating gate.

[0029] Referring to FIG. 7, a step of oxide CMP is performed to removethe oxide spacers 56 and portions of the isolation oxides 50. A layer ofinter-gate dielectric 46 is then formed over the floating gates 26 andisolation oxides 50. A second layer of polysilicon 48 is deposited overthe inter-gate dielectric layer 46 to form the control gate.Conventional CMOS manufacturing steps then follow to form a layer ofgate silicide or metal 58 and contacts (not shown).

[0030] In another embodiment of the present invention, the manufacturingprocess as described above relative to FIGS. 2-4 remains the same.Referring to FIG. 8, after the sections of the nitride layer 52 areremoved, a step of polysilicon chemical-vapor deposition (CVD) isperformed to deposit a layer of polysilicon 56′. Polysilicon spacer etchfollows to form a plurality of polysilicon spacers 56′ over the sectionsof the first polysilicon layer 26 and contiguous with the sidewalls ofthe isolation oxides 50. Using the polysilicon spacers 56′ as masks, thesections of the first polysilicon layer 26 is etched further to formadditional sections of the first polysilicon layer 26 as shown in FIG.9. Each of the further etched sections of the first polysilicon layer 26becomes a floating gate. A portion of each of the polysilicon spacers56′ is also removed during etching of the first polysilicon layer 26.The remaining steps of this embodiment are the same as those describedin reference to FIG. 7 above.

[0031] Other embodiments of the invention will be apparent to thoseskilled in the art from consideration of the specification and practiceof the invention disclosed herein. It is intended that the specificationand examples be considered as exemplary only, with a true scope andspirit of the invention being indicated by the following claims.

What is claimed is:
 1. An integrated circuit, comprising: a firstdual-floating gate memory cell having a first floating gate isolatedfrom a second floating gate for storing at least one bit of datum, and asecond dual-floating gate memory cell having a third floating gateisolated from a fourth floating gate for storing at least one bit ofdatum, wherein the first dual-floating gate memory cell and the seconddual-floating gate memory cell share a control gate, wherein the secondfloating gate of the first dual-floating gate memory cell shares anoxide layer with the third floating gate of the second dual-floatinggate memory cell, and wherein the oxide layer electrically insulates thesecond and third floating gates from the control gate.
 2. The integratedcircuit as claimed in claim 1, wherein one of the first, second, thirdand fourth floating gates has a vertical dimension greater than or equalto a horizontal dimension.
 3. The integrated circuit as claimed in claim1, wherein all of the first, second, third and fourth floating gateshave a vertical dimension greater or equal to than a horizontaldimension.
 4. The integrated circuit as claimed in claim 1, furthercomprising a first isolation oxide to isolate the first floating gatefrom the second floating gate.
 5. The integrated circuit as claimed inclaim 1, further comprising a second isolation oxide to isolate thethird floating gate from the fourth floating gate.
 6. A method formanufacturing a semiconductor device, comprising: defining a substrate;providing a dielectric layer over the substrate; depositing a firstlayer of polysilicon over the dielectric layer; providing a layer ofnitride over the first layer of polysilicon; forming a plurality ofcomposite structures, each having a section of the first polysiliconlayer and nitride layer; forming a plurality of diffused regions in thesubstrate between the plurality of composite structures; formingisolation oxides between the plurality of composite structures; removingthe sections of the nitride layer; forming a plurality of spacers overthe first polysilicon layer and contiguous with sidewalls of theisolation oxides; etching the first polysilicon layer with the pluralityof spacers acting as masks; removing the plurality of spacers; forming alayer of inter-gate dielectric over the etched first polysilicon layer;and forming a second polysilicon layer over the inter-gate dielectriclayer.
 7. The method as claimed in claim 6, wherein the step of forminga plurality of spacers includes forming a plurality of oxide spacers. 8.The method as claimed in claim 7, further comprising a step ofdepositing a layer of oxide.
 9. The method as claimed in claim 6,wherein the step of forming a plurality of spacers includes forming aplurality of polysilicon spacers.
 10. The method as claimed in claim 9,further comprising a step of depositing a layer of polysilicon.
 11. Themethod as claimed in claim 6, wherein the step of forming isolationoxides between the plurality of composite structures includes a step ofhigh-density plasma oxide deposition.
 12. The method as claimed in claim6, further comprising a step of chemical-mechanical polishing of theisolation oxides.
 13. A method for manufacturing a semiconductor device,comprising: defining a substrate; forming a dielectric layer over thesubstrate; depositing a first layer of polysilicon over the dielectriclayer; providing a layer of nitride over the first layer of polysilicon;etching the layer of nitride and the first layer of polysilicon to forma plurality of composite structures, each having a section of the firstpolysilicon layer and nitride layer; depositing a layer of oxide usinghigh-density plasma deposition over and between the plurality ofcomposite structures; removing the nitride layer; forming a plurality ofspacers over the first polysilicon layer; etching the first polysiliconlayer with the plurality of spacers acting as masks; removing theplurality of spacers; forming an inter-gate dielectric layer over theetched first polysilicon layer; and forming a second polysilicon layerover the inter-gate dielectric layer.
 14. The method as claimed in claim13, wherein the spacers are oxide spacers.
 15. The method as claimed inclaim 13, wherein the spacers are polysilicon spacers.
 16. The method asclaimed in claim 13, further comprising a step of chemical-mechanicalpolishing of the oxide layer.